The present invention relates to an improved binary calibration technique which is useful for calibrating timing of control and data signals in high frequency DRAM memory devices which clock in data on positive and negative going edges of a clock signal.
Memory devices are constantly evolving in the directions of faster speed and higher memory density. To this end, dynamic random access memory (DRAM) devices have evolved from simple DRAM devices to EDO to SRAM to DDR SDRAM to SLDRAM, the latter of which is the subject of much current industry interest. SLDRAM has a high sustainable bandwidth, low latency, low power, user upgradability and support for large hierarchical memory applications. It also provides multiple independent banks, fast read/write bus turn-around, and the capability for small fully pipelined burst.
One characteristic of SLDRAM is that it uses both the positive-and negative-going edges of a clock cycle to READ and WRITE data to the memory cells and to receive command and FLAG data from a memory controller.
An overview of SLDRAM devices can be found in the specification entitled xe2x80x9cSLDRAM Architectural and Functional Overview,xe2x80x9d by Gillingham, 1997 SLDRAM Consortium (Aug. 29, 1997), the disclosure of which is incorporated by reference herein.
Because of the required high speed operation of SLDRAM, and other contemporary memory devices, system timing and output signal drive level calibration at system initialization, such as at start-up or reset, is a very important aspect of the operation of such devices to compensate for wide variations in individual device parameters.
One of the several calibration procedures which is performed in current SLDRAM devices is a timing synchronization of clock signals CCLK (command clock signal) and DCLK (data clock signal) with data provided on incoming command paths CA and the FLAG path (for the CCLK signal) and on the data paths DQ (for the DCLK signal) so that incoming data is correctly sampled. Currently, a memory controller achieves this timing calibration at system initialization by sending continuous CCLK and DCLK transitions on those clock paths and transmitting inverted and non-inverted versions of a 15 bit repeating pseudo random SYNC sequence xe2x80x9c111101011001000xe2x80x9d on each of the data paths DQ, the command paths CA, and the FLAG path. The SLDRAM recognizes this pseudo random sequence by two consecutive ones xe2x80x9c1xe2x80x9d appearing on the FLAG bit and determines an optimal relative internal delay for CCLK and DCLK to optimally sample the known bit pattern. This optimal delay is achieved by adjusting the temporal position of the received data bits to achieve a desired bit alignment relative to the clock. This is accomplished by adjusting a delay in the receiving path of the received data until the received data is properly sampled by the clock and recognized internally. Once synchronization has been achieved, that is, the proper delays on the data receiving paths have been set, the memory controller stops sending the SYNC pattern and the SLDRAM, after all calibrations are completed, can be used for normal memory READ and WRITE access.
While the timing calibration described above, which is conducted at start-up and reset, has been found to perform adequately in most circumstances, there is a problem in that current SLDRAM devices capture incoming data on both positive and negative going transitions of the clock signals CCLK and DCLK. As a consequence, even when timing calibration is achieved it is not clear if alignment was achieved on a positive going or negative going clock edge. That is, the 15-bit synchronization pattern lacks any timing signature. It would be preferable to always align the data timing on one of the positive or negative going edges, e.g., the positive going edge, to simplify the command bit logic circuit. If circuit designers simplify the command bit logic circuit on the assumption that alignment is achieved on one of the positive and negative going edges, e.g., positive going edge, of the clock signal, achieving timing synchronization using the current 15 bit pseudo random pattern cannot guarantee that synchronization was achieved with respect to the correct, e.g., positive going, clock edge. If, for example, synchronization was achieved on the negative going edge of a clock signal when the circuitry is designed on the assumption that synchronization is achieved on a positive going edge, when data is later sampled during memory access the data sampling may be off by one bit. Moreover, because the 15-bit pseudo random pattern is repeated during the calibration process, there will be alternating times when it is properly synchronized on the correct clock transition, e.g., positive going, and then improperly synchronized with, e.g., a negative going transition, and there is no mechanism for knowing when the calibration process is completed, whether synchronization has been achieved in the positive or negative going transition of the clock. Thus, calibration may be achieved in the wrong phase, or edge, of the clock signal, leading to incorrect sampling of the data during memory access operations, or requiring additional complicated circuitry to ensure that incoming data is synchronized to the proper phase of the clock.
To overcome some of the shortcomings inherent in the 15 bit synchronization pattern, a 2N bit synchronization pattern has been proposed in U.S. application Ser. No. 09/568,155, filed May 10, 2000. Because the 2N bit synchronization pattern has an even number of bits, the calibration logic can achieve data synchronization on a desired phase of the associated clock. The synchronization pattern is preferably a 2N bit pattern which is produced by adding an additional bit to a 2Nxe2x88x92pseudo random bit pattern. The synchronization bit pattern employed is preferably 16 bits long.
While the 2N bit synchronization pattern has advantages over the 2Nxe2x88x921 bit synchronization pattern, it still takes a certain amount of time to achieve synchronization, also termed calibration, of all incoming data paths. Moreover, even with a 2N bit synchronization pattern, it is still possible that after all incoming data paths have been calibrated, there may still not be parallel alignment of the data bits across all incoming data paths, particularly if the range of possible timing compensation for the data paths is larger than a bit cycle. Still further, it is still possible to achieve synchronization on the undesired edge of the clock signal for some of the data paths.
The present invention utilizes the 2N bit synchronization pattern described in U.S. application Ser. No. 09/568,155, filed May 10, 2000 in a unique way to obtain a faster and more reliable calibration of the data paths. Since an even number of clock cycles are used to clock in the 2N bit synchronization pattern, the phase of the clock signal can be implied by the known order of the bits being captured. Typically, for a DDR/SLDRAM memory device the lowest common data burst rate is four (4) data bits. That is, four data bits at a time are serially sent on a data path. If the 2N bit synchronization pattern is generated with a known clock phase relationship from a memory controller to a memory device, then the data-to-clock phase alignment can be determined using simple decode logic to predict the next four bits from a just-detected four bits. If the succeeding four bit pattern does not match the predicted pattern, then the current data-to-clock alignment fails for a particular delay value adjustment in the data path undergoing alignment, and the delay in that data path is adjusted to a new value.
This process repeats until the decode logic correctly predicts the next four bits indicating that the delay value currently set for the data path is correct. In actual practice, the invention uses this prediction scheme over all possible values of delay in a data path and develops a xe2x80x9cwindowxe2x80x9d of acceptable delay values which cause correct prediction of the next four bits of the synchronization pattern. Then, a delay value is set which is at or near the center of the window of acceptable delay values.
The invention also ensures that data alignment will occur to a desired edge of the clock signal, e.g., a positive going edge, by forcing a failure of all predicted four bit patterns which are associated with an undesired edge, e.g., a negative going edge, of the clock signal.